Effect of thermal cycle loadings on mechanical properties and thermal conductivity of a porous lead-free solder joint

Abstract

© 2011-2012 IEEE. This paper demonstrates to what extent the number of thermal cycles affects the mechanical properties as well as the thermal conductivity of a porous solder joint in an insulated-gate bipolar transistor discrete. The blind mode voids were used for a finite-element method (FEM) simulation to obtain the results close to the actual conditions. The FEM results indicate that the concentration of creep strain at the interface of the solder/chip is in its maximum value, and it slightly decreases along with the depth of the solder layer. FEM also reveals that the boundaries of voids act as critical regions for strain concentration. An upward in the number of thermal cycles also leads to the void growth and coalescence process. The enhancement of void volume from 0 to 15 cycles is about 4% volume of the solder layer. Moreover, scanning electron microscope micrographs approve the FEM results and show the void growth and the damage accumulation during thermal cycling. The thermal analyses indicate that the increase in thermal cycles (creep strain) leads to a significant rise in thermal impedance. This event can be due to the increase in the void volume of the solder layer leading to the decrease in the effective area of heat path.