FPGA implementation of LTE turbo decoder using MAX-log MAP algorithm

dc.contributor.author	Belov V.
dc.contributor.author	Mosin S.
dc.date.accessioned	2018-04-05T07:10:27Z
dc.date.available	2018-04-05T07:10:27Z
dc.date.issued	2017
dc.identifier.uri	http://dspace.kpfu.ru/xmlui/handle/net/130457
dc.description.abstract	© 2017 IEEE. Implementation of an efficient turbo decoder with low complexity, short delay and insignificant performance degradation is currently a quite challenging task. The paper presents an implementation of a 3GPP TS 36.212 LTE turbo decoder. The design of the turbo decoder has been optimized to achieve efficient FPGA resource utilization. This design can be useful for applications, which is critical to resource utilizations, but do not need high throughput.
dc.subject	BCJR
dc.subject	FPGA implementation
dc.subject	LTE turbo decoder
dc.subject	MAP
dc.subject	MAX-log MAP
dc.subject	Turbo decoder
dc.title	FPGA implementation of LTE turbo decoder using MAX-log MAP algorithm
dc.type	Conference Paper
dc.collection	Публикации сотрудников КФУ
dc.source.id	SCOPUS-2017-SID85027076676

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Публикации сотрудников КФУ Scopus [24551]
Коллекция содержит публикации сотрудников Казанского федерального (до 2010 года Казанского государственного) университета, проиндексированные в БД Scopus, начиная с 1970г.